FIG. 2 shows a prior art semiconductor differential amplifier. In FIG. 2, the reference characters Q1 and Q2 designate a third and a fourth load P channel MOS transistor having an equal gate width and gate length, respectively. The reference characters Q3 and Q4 designate a first and a second driving N channel MOS transistor having an equal gate width and gate length, respectively. The reference characters D and D designate a pair of input terminals. The reference character N designates a connection node of the drains of the transistors Q1 and Q3. The reference character RD designates a connection node of the drains of the transistors Q2 and Q4, RD being an output terminal of this differential amplifier. The reference character Q5 designates a power cut N channel MOS transistor. The reference character SE designates a power cut internal signal. The reference character Vcc designates a power supply voltage, and the reference character GND designates a ground voltage.
The device operates as follows.
Supposing that the power cut internal signal SE is at "H" level, the transistor Q5 is turned on an the differential amplifier is activated.
In such a state, the transistor Q1 has a common gate drain, and therefore the variation of the voltage of the node N is small relative to the variation of the voltage of the input terminal D. The node N also functions as a gate input of the transistor Q2 and if the voltages of the input terminals D and D are equal to each other, the output at node RD will be the same voltage as that of the node N. The voltages of the input terminals D and D and the sizes of the transistors Q1 to Q4 are established such that the transistors Q2 and Q4 enter an equilibrium state at the pentode region. In this state, when a slight voltage difference arises between input terminals D and D the transistors Q2 and Q4 go out of equilibrium, thereby resulting in a large variation of the voltage at the output node RD.
Furthermore, when the power cut internal signal SE is at an "L" level thereby to turn off the transistor Q5, the quiescent currents which penetrate through the transistors Q1 to Q3, or the transistors Q2 to Q4, respectively, are eliminated, whereby the device enters into the power cut state.
In the prior art semiconductor differential amplifier of such construction, the voltage difference between the input terminal pair D and D is received only by the N channel MOS transistor, and thus the ability of pulling up the voltage at the node N or the output RD to the power supply voltage side is small, therefore it is not possible to obtain a high sensitivity against a small voltage difference between the terminal pair D and D.